The challenges in fabricating transistors with diminutive feature sizes in the nanometer regimes have resulted in significant variations in key transistor parameters, such as transistor channel length, gate-oxide thickness, and threshold voltage. This manufacturing variability can  cause significant performance and power deviations from nominal values in identical hardware designs. Designing for the worst case scenario may no longer be a viable solution, especially when the variability encountered in the new process technologies becomes very significant and causes substantial percentage deviations from the nominal values. Increasing cost sensitivity in the embedded system design methodology makes designing for the worst case infeasible. Further, worst-case analysis without taking the probabilistic nature of the manufactured components into account can also result in an overly pessimistic estimation in terms of performance.  As a result, a shift in the design paradigm, from today’s worst-case deterministic design to statistical or probabilistic design, is critical for deep sub-micron VLSI design.

The goal of the project includes:

• EDA solutions: developing design automation techniques to perform statistical analysis and variation-aware synthesis for nanometer VLSI systems.
• Circuit/Architecture solutions: developing design techniques for variation tolerant circuits/architecture.

Project Sponsors:

• NSF CAREER: Process Variation Aware Embedded MPSoC Synthesis
• SRC: Statistical Behavioral Synthesis for Nanometer VLSI Chips

Students:

• Feng Wang (Graduated in 2008, now with Qualcomm)
• Balaji Vaidyanathan (Graduated in 2009, now with TSMC)
• Yibo Chen
• Dimin Niu