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2006

[DAC2006] S. Srinivasan, M. Prasanth, S. Karthink, Yuan Xie, N. Vijaykrishnan, "FLAW: FPGA Lifetime Awareness", Proceed-ings of the 43rd Design Automation Conference (DAC), pp. 630-635, July. 2006. (209 papers accepted out of 865 submissions. 24% acceptance rate)
[ISCA2006] F. Li, C. Nicopoulos, T. Richardson, Yuan Xie, N. Vijaykrishnan, M. Kandemir, "Design and Management of 3D Chip Multiprocessors using Network-in-memory", Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 130-141, June. 2006. (31 papers accepted out of 234 submissions. 13% acceptance rate)
[JETC2006] Yuan Xie, Gabriel Loh, Bryan Black, and Kerry Bernstein, "Design Space Exploration for 3D Architecture", ACM Journal of Emerging Technologies for Computer Systems, Vol. 2. No. 2, pp.65-103, April 2006
[SELSE2006] R. Ramanarayanan, R. Krishnan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, "Temperature and Voltage Scaling Effects on Electrical Masking", Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006
[SELSE2006] B. Vaidyanathan, Yuan Xie, N. Vijaykrishnan, "Soft Error Analysis and Optimizations of C-elements in Asynchronous Circuits", Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006
[SELSE2006] Feng Wang, Yuan Xie, "An Accurate and Efficient Model of Electrical Masking Effect for Soft Errors in Combinatorial Logic", Proceedings of the Second Workshop on System Effects of Logic Soft Errors (SELSE), April 2006
[ISQED2006] Wei-lun Hung, G. Link, Yuan Xie, N. Vijaykrishnan, M. J. Irwin, "Interconnect and Thermal-aware Floorplanning for 3D Microprocessors", Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 98-104, March. 2006. (93 papers accepted out of 256 submissions. 36% acceptance rate)
[ISVLSI2006] M. Mutyam, M. Eze, N. Vijaykrishnan, Yuan Xie, "Delay and Energy Efficient Data Transmission for On-Chip Buses", Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 355-360, March 2006
[DATE2006] Feng Wang, Yuan Xie, N. Vijaykrishnan and M. J. Irwin, "On-chip Bus Thermal Analysis and Optimization", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 850-855, March 2006.(233 papers accepted out of 834 submissions. 28% acceptance rate)
[ISVLSI2006] Feng Wang, Yuan Xie, K. Bernstein and Y. Luo, "Dependability Analysis of Nano-scale FinFET Circuits", Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 399-404, March 2006
[ISVLSI2006] S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie, "Reliability-Aware SOC Voltage Islands Partition and Floorplan", Proceedings of the IEEE Computer Society Annual Symposium on VLSI Design (ISVLSI), pp. 343-348, March 2006
Degalahal, V., R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, "Effect of Power Optimizations on Soft Error Rate", IFIP Series on VLSI-SoC. pp. 1-20, 2006. Edited by R. Reis. Springer
[IEEECOMPUTER2006] N. Vijaykrishnan and Yuan Xie, "Reliability Concerns in Embedded System Designs", IEEE Computer, Vol. 39, No.1, pp.118-120, January 2006
[TVLSI2006] Yuan Xie, W.Wolf, and H. Lekatsas, "Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 14. No. 5, pp.525-536, January. 2006
[ASPDAC2006] O. Ozturk, F. Wang, M. Kandemir, Yuan Xie, "Optimal Topology Exploration for Application-Specific 3D Archi-tectures", Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 390-395, Jan. 2006. (135 papers accepted out of 432 submissions. 31% acceptance rate)
[VLSID2006] Ramanarayanan, R., J. S. Kim, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, "SEAT-LA: A Soft Error Analysis toolfor Combinational Logic", Proceedings of IEEE International Conference on VLSI Design, pp. 499-502, Jan. 2006. (26.8% acceptance rate for regular papers (88 out of 328 submissions))
[VLSID2006] T. Richardson, C. Nicopoulos, D. Park, N. Vijaykrishnan, Yuan Xie, C. R. Das, "A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks", Proceedings of IEEE International Conference on VLSI Design, pp. 499-502, Jan. 2006. (26.8% acceptance rate for regular papers)

2005

[ICCD2005] W-L. Hung, G. Link, Yuan Xie, N. Vijaykrishnan, N. Dhanwada, J. Conner, "Temperature-Aware Voltage Islands Architecting in System-on-Chip Design", Proceedings of IEEE International Conference on Computer Design (ICCD), pp.689-696, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)
[ICCD2005] S. K. Narayanan, G. Chen, M. Kandemir, Yuan Xie, "Temperature-Sensitive Loop Parallelization for Chip Multi-processors", Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 677-682, Oct. 2005. (101 outof 313 submissions, 32% acceptance rate)
[ASICON2005] T. Richardson and Yuan Xie, "Evaluation of Thermal-Aware Design Techniques for Microprocessors", Proceedings of IEEE International Conference on ASICs, pp.62-65, Oct. 2005
[ICCD2005] Y-F. Tsai, Yuan Xie, N. Vijaykrishnan, M. J. Irwin, "Three-Dimensional Cache Design Exploration Using 3DCacti", Proceedings of IEEE International Conference on Computer Design (ICCD), pp.519-524, Oct. 2005. (101 out of 313 submissions, 32% acceptance rate)
[ISVLSI2005] D. Hostetler and Yuan Xie, "Adaptive Power Management in Software Radios Using Resolution Adaptive Analogto Digital Converters", Proceedings of IEEE International Symposium on VLSI (ISVLSI), pp. 186-191, May. 2005
[ISQED2005] S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, "An ILP Formulation for Reliability-Oriented High-Level Synthesis", Proceedings of International Symposium on Quality Electronic Design (ISQED), pp.364-369, Mar.2005. (83 out of 222 submissions, 37% acceptance rate)
[ISQED2005] S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, "Reliability-Centric Hardware/Software Co-design", Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 364-369, Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)
[DATE2005] S. Tosun, N. Mansouri, E. Arvas, M. Kandemir, Yuan Xie, "Reliability-centric High-level Synthesis", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1258-1263, March 2005. ( 176 papers accepted out of 825 submissions. 21% acceptance rate)
[DATE2005] Y-F Tsai, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, "Leakage-Aware Interconnect for On-Chip Network", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp.230-231, March 2005.( 21%acceptance rate)
[DATE2005] S. Yang, W. Wolf, N. Vijaykrishnan, Yuan Xie, "Power Attack Resistant Crypto Design: A Dynamic Voltage and Frequency Switching Approach", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 64-69, March 2005. ( 21% acceptance rate)
[ASPDAC2005] J.Conner,Yuan Xie, M. Kandemir, R. Dick, G. Link, "FD-HGAC: A Hybrid Heuristic/Genetic Algorithm Hard-ware/Software Co-synthesis Framework with Fault Detection", Proceedings of the Asia South Pacific Design AutomationConference (ASP-DAC)., pp. 709-712, Jan. 2005. (99 regular papers accepted out of 692 submissions (14.3%))
[DATE2005] W-L. Hung, Y. Xie, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Thermal-aware task allocation and scheduling for embedded systems", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 898-899, March 2005. ( 21% acceptance rate)
[ISQED2005] W-L. Hung, Y. Xie, N. Vijaykrishnan, C. Addo-Quaye, T. Theocharides, and M. J. Irwin, "Thermal-Aware Floorplanning Using Genetic Algorithms", Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 634-639, Mar. 2005. (83 out of 222 submissions, 37% acceptance rate)
[ASICON2005] Luo, R., Luo, L., Yang, H., & Xie, Y, "An instruction-level analytical power model for designing the low power systems on a chip", ASIC, 2005. ASICON 2005. 6th International Conference On. Vol. 2. IEEE, 2005
[ASICON2005] Ding Qian, Rong Luo, and Yuan Xie, "Impact of process variation on soft error vulnerability for nanometer VLSI circuits", ASIC, 2005. ASICON 2005. 6th International Conference On. Vol. 2. IEEE, 2005
[VLSID2005] Y-F. Tsai, N. Vijaykrishnan, M. J. Irwin, Yuan Xie, "Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty", Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 374-379, Jan. 2005. (97 regularpapers accepted out of 352 submissions (28%))
[DATE2005] Shengqi Yang, Wayne Wolf, N.Vijaykrishnan, D.N.Serpanos and Yuan Xie, "Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach", Proceedings of the conference on Design, Automation and Test in Europe-Volume 3. IEEE Computer Society, 2005
[ASPDAC2005] S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie, "Low-Leakage Robust SRAM Cell Design for Sub-100nm Technologies", Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC)., pp. 539-544, Jan. 2005. 14.3% acceptance rate for regular papers (99 regular papers accepted out of 692 submissions (14.3%))
[VLSID2005] S. Yang, W. Wolf, W. Wang, N. Vijaykrishnan, Yuan Xie, "Accurate Stacking Effect Macro-Modeling of LeakagePower in Sub-100nm Circuits", Proceedings of the 18th International Conference on VLSI Design (VLSID), pp. 165-170, Jan. 2005. (97 regular papers accepted out of 352 submissions (28%))

2004

[ICCAD2004] S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Yuan Xie, M. J. Irwin, "Improving Soft-error Tolerance of FPGA Configuration Bits", Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 107-110, Nov. 2004.(24% acceptance rate)
[ICCD2004] W-L Hung, C. Addo-Quaye, T. Theocharides, Yuan Xie, N. Vijaykrishnan, M. J. Irwin, "Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture", Proceedings of IEEE International Conference on Computer Design (ICCD), pp. 430-437, Oct. 2004. (84 out of 226 submissions, 37% acceptance rate.)
[ASAP2004] Yuan Xie, L. Li, M. Kandemir, N. Vijaykrishnan, M. J. Irwin, "Reliability-aware Co-synthesis for Embedded Systems", Proceedings of IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP), pp. 41-50, Sept. 2004
[ISLPED2004] W-L. Hung,Yuan Xie, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, "Total Power Optimization Through Simul-taneously Multiple-VDD Multiple-VTH Assignment and Device Sizing With Stack Forcing", Proceedings of International Symposium on Low Power Electronics and Design (ISLPED 2004), pp. 144-149, Aug. 2004. 34% acceptance rate)
[GLSVLSI2004] W. Xu, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, "Design of a Nanosensor Array Architecture", Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pp. 298-303, Apr. 2004. (23 full papers accepted out of 235 submissions, 10% rate)
[ISQED2004] V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, "The Effect of Threshold Voltages on the Soft Error Rate", Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 503-508, Mar. 2004. (49 papers accepted out of 148 submissions, 33%)
[DATE2004] C-H. Lin, W. Wolf, and Yuan Xie, "LZW-based Code Compression for VLIW Embedded Systems", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp.76-81, Feb.2004.(181 papers accepted out of 780 submissions (23%))

2003

[JCSC2003] Yuan Xie, Jiang Xu, W.Wolf, "Augmenting Platform-based Design with Synthesis Tools", Journal of Circuits, Systems and Computers, Vol. 14. No. 5, pp.525-536, April. 2003
[ASICON2003] Yuan Xie, "Analysis of Two Code Compression Algorithms for Embedded Systems", Proceedings of International Conference on ASIC (ASICON), pp. 773-776. Oct. 2003
[DATE2003] Yuan Xie, W. Wolf, and H. Lektasas, "Profile-driven Code Compression", Proceedings of IEEE International Confer- ence on Design Automation and Test in Europe (DATE), pp. 76-81, Mar. 2003. (152 out of 590 submissions (25%))
[DCC2003] Xie, Yuan, Wayne Wolf, and Haris Lekatsas, "Code compression using variable-to-fixed coding based on arithmetic coding", Data Compression Conference, 2003. Proceedings. DCC 2003. IEEE, 2003: 382-391

2002

[ISSS2002] Yuan Xie, W. Wolf, and H. Lektasas, "Code Compression for VLIW Using Variable-to-fixed Coding", Proceedings of Fifteenth International Symposium on System Synthesis (ISSS 2002), pp. 138-143, Oct. 2002. (24 out of 71 submissions (33%))

2001

[MICRO2001] Yuan Xie, W. Wolf, and H. Lektasas, "A Code Decompression Architecture for VLIW Processors", Proceedings of the Thirty-Fourth International Symposium on Microarchitecture (MICRO-34). pp. 66-75. (29 out of 144 submissions, 20% acceptance rate)
[ASICON2001] Yuan Xie, W. Wolf, and H. Lektasas, "Compression Ratio and Decompression Overhead Tradeoffs in Code Com- pression for VLIW Architectures", Proceedings of the Fourth International Conference on ASIC (ASICON). Best Paper Award

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