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2009

[TDCS2009] R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "Modeling Soft Errors at Device and Logic Level for Combinational Circuits", IEEE Transactions on Dependable and Secure Computing (TDCS)., Vol. 6, No. 3, pp.202-216, June 2009
[ISCA2009] Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie, "Hybrid Cache Architecture with Disparate Memory Technologies", Proceedings of International Symposium on Computer Architecture (ISCA), pp.34-45, June. 2009
[NOCS2009] Luca P. Carloni, Partha Pande, and Yuan Xie, "Networks-on-chip in emerging interconnect paradigms: Advantages and challenges", Proceedings of 3rd ACM/IEEE Intl. Symp. on Networks-on-chip, pp. 93-102. May. 2009
[DATE2009] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization", Proceedings of Design Automation and Test in Europe (DATE), pp. 324-333. April. 2009
[DATE2009] Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie, "Power and Performance of Read-write aware hybrid caches with non-volatile memories", Proceedings of Design Automation and Test in Europe (DATE), pp. 737-742. April. 2009
[ISQED2009] Balaji Vaidyanathan, Anthony Oates, Yuan Xie, Yu Wang, "NBTI-Aware Statistical Circuit Delay Assessment", Proceedings of the 2009 10th International Symposium on Quality of Electronic Design (pp. 13-18). IEEE Computer Society.
[ISQED2009] Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang, "On the efficacy of Input Vector Control to mitigate NBTI effects and leakage power", Proceedings of the 2009 10th International Symposium on Quality of Electronic Design (pp. 19-26). IEEE Computer Society.
[HPCA2009] Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen, "A novel architecture of the 3D stacked MRAM L2 cache for CMPs", Proceedings of High Performance Computer Architecture (HPCA), pp. 239-249. Feb. 2009. (19% acceptance rate(34/185))
[ICCD2009] Al Maashri, A., G. Sun, X. Dong, V. Narayanan, Y. Xie, "3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis", Computer Design, 2009. ICCD 2009. IEEE International Conference on (pp. 254-259). IEEE.
[3DIC2009] Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, and Mary Jane Irwin, "Arithmetic unit design using 180nm TSV-based 3D stacking technology", 3D System Integration Conference (3DIC) 2009 (pp. 1-4). IEEE.
Yuan Xie, Jason Cong, Sachin Sapatnekar, "Three-dimensional IC: Design, CAD, and Architecture", Springer. 2009
Yuan Xie, N. Vijaykrishnan, Chita Das, "3D Network-on-chip Architecture", Three-dimensional IC: Design, CAD, and Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009
Yuan Xie, Xiangyu Dong, "System-level Cost Analsysis and Design Exploration for 3D ICs", Three-dimensional IC:Design, CAD, and Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009
[ASPDAC2009] Yibo Chen and Yuan Xie, "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches", Proceedings of the 2009 Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 73-78. IEEE.
[ASPDAC2009] Mike Debole, Wenping Wang, Yu Wang, Yuan Xie, Vijay Nayaranan, Yu Cao, "A Framework for Estimating NBTIDegradation of Microarchitectural Components", Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 455-460. Jan. 2009. (32% acceptance rate(116/355))
[ASPDAC2009] Mike Debole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan, "A Criticality-Driven Microarchitectural ThreeDimensional (3D) Floorplanner", Proceedings of the 2009 Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 763-768, Jan. 2009, IEEE (32% acceptance rate(116/355))
[ASPDAC2009] Xiangyu Dong and Yuan Xie, "System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)", Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 234-241, Jan. 2009. Best Paper Award Nomination. (32% acceptance rate(116/355))
[3DIC2009] Brent Hollosi, Tao Zhang, Ravi S. P. Nair, Yuan Xie, Jia Di, and Scott Smith, "Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs", 3D System Integration Conference (3DIC), pp. 1-5, 2009. IEEE
[IEEECOMPUTERS2009] Mutyam, M., Wang, F., Krishnan, R., Narayanan, V., Kandemir, M., Xie, Y., & Irwin, M. J, "Process Variation-Aware Adaptive Cache Architecture and Management", Computers, IEEE Transactions on 58.7 (2009): 865-877
J. Ouyang, G. Sun, Y. Chen, L. Duan, T. Zhang, Y. Xie, "Design and Implementation of Three Dimensional Arithmetic Units",
[ISLPED2009] Guangyu Sun, Xiaoxia Wu, Yuan Xie, "Exploration of 3D Stacked L2 Cache Design for High Performance and Efficient Thermal Control", Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design (ISLPED), pp. 295-298 . ACM, 2009
[MTDT2009] B. Vaidyanathan, Y. Wang, Y. Xie, "Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache", 2009 IEEE International Workshop on Memory Technology, Design, and Testing, pp.65-70, 2009
[ASPDAC2009] Feng Wang, Andres Takach, Yuan Xie, "Variation-aware resource sharing and binding in behavioral synthesis", Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 79-84, Jan. 2009
[IEEED&T2009] Yuan Xie and Yibo Chen, "Statistical High-Level Synthesis under Process Variability", IEEE Design & Test of Computers 4 (2009): 78-87.
[NANOARCH2009] Yuan Xie, Soumya Eachempati, Aditya Yanamandra, Vijaykrishnan Narayanan, Mary Jane Irwin, "Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network", Nanoscale Architectures, 2009. NANOARCH'09. IEEE/ACM International Symposium on (pp. 51-56). IEEE.

2008

[JRNC2008] C. Celik, K.Unlu, K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, M. J. Irwin, Y. Xie, "Thermal Neutron Induced Soft Error Rate Measurement in Semiconductor Memories and Circuits", Journal of Radioanalytical and Nuclear Chemistry.,Vol. 278, No.2, pp.509-512, Nov 2008
[ICCAD2008] P. Mangalagiri, S. Bae, R. Krishnan, Yuan Xie, N. Vijaykrishnan, "Thermal-Aware Reliability Analysis for Platform FPGAs", Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 722-727, Nov. 2008. (122 out of458 submissions, 27% acceptance rate)
[ICCD2008] Xiaoxia Wu, Yibo Chen, Krish Chakrabarty, and Yuan Xie, "Test-Access Mechanism Optimization for Core-Based Three-Dimensional SOCs", Proceedings of International Conference on Computer Design (ICCD), pp.212-218 Oct. 2008
[SOCC2008] Yibo Chen, Feng Wang, Yuan Xie, "ILP-based Scheme for Timing Variation-aware Scheduling and Resource Binding", Proceedings of System-on-Chip Conference, pp.27-30, Sept. 2008
[SOCC2008] Jin Ouyang, Yuan Xie, "Power Optimization for FinFET-based Circuits Using Genetic Algorithms", Proceedings of System-on-Chip Conference, pp. 211-214, Sept. 2008
[TVLSI2008] Shengqi Yang, W. Wang, W. Wolf, Yuan Xie, N. Vijaykrishnan, "Case Study of Reliability-Aware and Low-Power Design", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 16, Issue 7, pp.861-873, July 2008
[DAC2008] Xiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory", Proceedings of Design Automation Conference (DAC),pp.554-559, June. 2008. (138 out of 639 submissions, 21% acceptance rate)
[ASAP2008] Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam, "Thermal-aware Design Considerations for Application-Specific Instruction Set Processor", Proceedings of International Symposium on Appication Specific Processors, pp. 63-68, June. 2008. (19 out of 64 submissions, 29% acceptance rate)
[ISCA2008] Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das, "MIRA: A Multi-Layered On-Chip Interconnect Router Architecture", Proceedings of International Symopsium on Computer Architecture (ISCA), Vol. 36, No. 3, pp. 251-261, June. 2008. (37 out of 259 submissions, 14% acceptance rate)
[3DIC2008] Xiangyu Dong, Xiaoxia Wu, Yuan Xie, "Cost Analysis and Cost-driven EDA flow for 3D ICs", in Proceedings of 3D-IC Conference, May. 2008
[TDCS2008] S. Srinivasan, R. Krishnan, P. Mangalagiri, Yuan Xie, and N. Vijaykrishnan, "Towards Increasing FPGA Lifetime", IEEE Transactions on Dependable and Secure Computing (TDCS), Vol. 5, Issue 2, pp.115-127 Apr-Jun 2008
[TVLSI2008] Yuh-fang Tsai, Feng Wang, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin, "Design Space Exploration for Three-Dimensional Cache", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.16, Issue 4, pp.444-455, Apr. 2008
[DATE2008] Feng Wang, Guangyu Sun, Yuan Xie, "A Variation Aware High Level Synthesis Framework", Proceedings of Design Automation and Test in Europe (DATE), pp.1063-1068, Mar. 2008. (198 out of 839 submissions, 23% acceptance rate)
[ASPDAC2008] Feng Wang, Xiaoxia Wu, Yuan Xie, "Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning", To appear in Proceedings of Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 2-9, Jan. 2008. Best Paper Award. (29% acceptance rate for regular papers (100/351))
[ITSW2008] Xiaoxia Wu, P. Falkenstern, K. Chakrabarty, Yuan Xie, "Scan-chain Design and Optimization for 3D ICs", International Test Syntehsis Workshop, 2008

2007

[ICCAD2007] Feng Wang, Xiaoxia Wu, C. Nicopoulos, Yuan Xie, N. Vijaykrishnan, "Variation-aware Task Allocation and Scheduling for MPSoC", Proceedings of International Conference on Computer Aided Design (ICCAD), pp. 138-149, Nov. 2007. (139 out of 510 submissions, 27% acceptance rate)
[TVLSI2007] Chang-hong Lin, Yuan Xie, and W.Wolf, "Code Compression for VLIW Embedded Systems Using a Self-Generating Table", IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 10., pp.1160-1171, Oct. 2007
[ICCD2007] S. Srinivasan, P. Mangalagiri, Yuan Xie, N. Vijaykrishnan, "FPGA Routing Architecture Analysis Under Variations", Proceedings of International Conference on Computer Design (ICCD), pp.152-157, Oct.2007. (88 out of 259 submissions, 33% acceptance rate)
[ICCD2007] Xiaoxia Wu, Paul Falkenstern, and Yuan Xie, "Scan Chain Design for Three-dimentional(3D) ICs", Proceedings of International Conference on Computer Design (ICCD), pp.208-214, Oct. 2007. (88 out of 259 submissions, 33% acceptance rate)
[PATMOS2007] H. Luo, Y. Wang, K. He, R. Luo, H. Yang, and Yuan Xie, "A Novel Gate-level NBTI Delay Degradation Model with Stacking Effect", Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS), pp. 160-170. Springer Berlin Heidelberg. Sept. 2007
[TVLSI2007] Yuan Xie, W.Wolf, and H. Lekatsas, "Code Decompression Unit Design for VLIW Embedded Processors", IEEE Transactionson Very Large Scale Integration Systems (TVLSI), Vol. 15. No. 8, pp.975-980, Aug. 2007
[MSE2007] Alex K. Jones, Steven Levitan, Rob A. Rutenbar, and Yuan Xie, "Collaborative VLSI-CAD Instruction in the Digital Sandbox", Proceedings of IEEE International Conference on Microelectronic Systems Education, pp. 141-142, June 2007
[ISCA2007] J. Kim, C. Nicopoulos, D. Park, R. Das, Yuan Xie, N. Vijaykrishnan, C. Das, "A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures", Proceedings of the Annual International Symposium on Computer Architecture (ISCA), pp. 138-149, June 2007. (46 papers accepted out of 204 submissions. 23% acceptance rate)
[MICRO2007] Gabriel Loh, Yuan Xie, and Bryan Black, "Processor Design in Three-Dimensional Die-Stacking Technologies", IEEE Micro, Vol. 27. No. 3, pp.31-48, May/June 2007
[DATE2007] Feng Wang, Yuan Xie, and Hai Ju, "A Novel Criticality Computation Method in Statistical Timing Analysis", Proceedings of IEEE International Conference on Design Automation and Test in Europe (DATE), pp. 1611-1616, April 2007.(208 papers accepted out of 933 submissions. 22% acceptance rate)

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