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2011

[DATE2011] Jishen Zhao, Xiangyu Dong, and Yuan Xie, "An Energy-Efficient 3D CMP Design with Fine-Grained Voltage Scaling", In Proceedings of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp.539-542, 2011
[CODES+ISSS2011] Qiaosha Zou, Yibo Chen, Alan Su, Yuan Xie, "System-level design space exploration for three-dimensional (3D) SoCs", Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2011,  385-388, (Invited Paper)

2010

[TACO2010] Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie, "Hybrid Cache Architecture with Disparate Memory Technologies", ACM Transactions on Architecture and Code Optimization (TACO). Vol. 7, No. 3, December 2010
[DAC2010] Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie, "Impact of Process Variations on Emerging Memristor", Proceedings of Design Automation Conference (DAC). 2010. pp. 877-882. (24% acceptance rate)
[DAC2010] Xiaoxia Wu, Guangyu Sun, Reetuparna Das, Yuan Xie, Jian Li, Chita R. Das, "Cost-driven 3D Integration withInterconnect Layers", Proceedings of Design Automation Conference (DAC). 2010. pp.150-155. (24% acceptance rate)
[DAC2010] Jishen Zhao, Xiangyu Dong, Yuan Xie, "Cost-Aware Three-Dimensional (3D) Many-Core Multiprocessor Design", Proceedings of Design Automation Conference (DAC). 2010. pp.126-131. (24% acceptance rate)
[TVLSI2010] Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, and Kaushik Roy, "Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance", IEEE Transactions on VLSI (TVLSI), Vol 18, No. 11, pp. 1621-1624, Nov. 2010
[ICCAD2010] Yibo Chen, Dimin Niu, Yuan Xie, Krish Chakrabarty, "Cost-Effective Integration of Three-Dimensional (3D) ICs Emphasizing Testing Cost Analysis", Proceedings of Int. Conf. on CAD (ICCAD), Nov, 2010. pp. 471-476
[SC2010] Xiangyu Dong, Yuan Xie, Norm Jouppi, Naveen Muralimanohar, "Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support", Proceedings of the 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis (pp. 1-11). IEEE Computer Society.
[ITC2010] Li Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu, "Modeling TSV Open Defects in 3D-Stacked DRAM", Test Conference (ITC), 2010 IEEE International (pp. 1-9). IEEE.
[MICRO2010] Jin Ouyang and Yuan Xie, "LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support", Proceedings of Intl. Symp. on Microarchitecture (MICRO 2010), pp.351-356, 2010
[3DIC2010] Jing Xie, Xiangyu Dong, Yuan Xie, "3D Memory Stacking for Fast Checkpointing/Restore Applications", Proceedings of IEEE International 3D System Integration Conference (3DIC), 2010
[3DIC2010] Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng,Yong-long Lin,, "A 3D SoC Design for H.264 Application With On-Chip DRAM Stacking", Proceedings of IEEE International 3D System Integration Conference (3DIC), 2010
[CICC2010] Tao Zhang, Kui Wang, Yi Feng, Lian Duan, Xiaodi Song, Yuan Xie, Xu Cheng, Yong-long Lin,, "A Customized Designof DRAM Controller for On-Chip 3D DRAM Stacking", Proceedings of Custom IC Conference (CICC 2010), 2010
[MICROELECTRONJ2010] Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie, "Test-access mechanism optimization for core-based three-dimensional SOCs", Microelectronics Journal, Volume 41 Issue 10, pp. 601-615, Oct. 2010
[SiPS2010] Matt Poremba, Yuan Xie, Marilyn Wolf, "Accelerating Adaptive Background Subtraction with GPU and CBEA Architecture", Proceedings of IEEE Workshop on Signal Processing Systems (SiPS), pp.305-310, Oct. 2010
[ISLPED2010] Yibo Chen, Jishen Zhao, Yuan Xie, "3D-NonFAR: Three-Dimensional Non-Volatile FPGA ARchitecture Using Phase Change Memory", Proceedings of Intl. Symp. Low Power Electronic Devices (ISLPED). August, 2010. pp.55-60.(25% acceptance rate)
[MICRO2010] Gabe Loh, Yuan Xie, "3D Stacked Microprocessor: Are We There Yet?", IEEE Micro, Volume 30 Issue 3, pp. 60-64, May. 2010
[DATE2010] Yongsoo Joo, Dimin Niu, Guangyu Sun, Xiangyu Dong, Yuan Xie, "Energy- and Endurance-Aware Design of Phase Change Memory Caches", Proceedings of Design Automation and Test in Europe (DATE). 2010. pp.136-141. (25% acceptance rate)
[JVSP2010] Wei-lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut Kandemir, and Mary Jane Irwin, "Total Power Optimization for Combinational Logics Using Genetic Algorithms", Journal of VLSI Signal Processing. Vol. 58, No. 2, pp.145-160, Feb. 2010
[TCAD2010] Dong, Xiangyu, Jishen Zhao, and Yuan Xie, "Fabrication cost analysis and cost-aware design space exploration for 3-D ICs", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 29.12 (2010): 1959-1972
[ASPDAC2010] Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, "Parametric Yield Driven Resource Binding in Behavioral Synthesis with Multi-Vth/Vdd Library", Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2010. pp.781-786. (33% acceptance rate(115/340)) (Best Paper Nomination)
[ASPDAC2010] Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, "Minimizing Leakage Power in Aging-Bounded High-level Synthesis with Design Time Multi-Vth Assignment", Proceedings of Asia and South-Pacific Design Automation Conference (ASP-DAC). 2010. pp.689-694. (33% acceptance rate(115/340))
[ASPDAC2010] Paul Falkstern, Yao-wen Chang, Yuan Xie, Yu Wang, "Three Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis", Proceedings of the 2010 Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 169-174. IEEE
[ASPDAC2010] Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie, "Energy and Performance Driven Circuit Design for Emerging Phase-Change Memory", Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific (pp. 193-198). IEEE.
[ISLPED2010] Niu, Dimin, Yiran Chen, and Yuan Xie, "Low-power Dual-element Memristor Based Memory Design", Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design (pp. 25-30). ACM.
[ICCAD2010] Jin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie, "Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip", Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2010, pp. 477-482. IEEE
[HPCA2010] Guangyu Sun, Yongsoo Joo, Yibo Chen, Yuan Xie, Yiran Chen, Helen Li, "A Hybrid Solid-State Storage Architecture for Performance, Energy Consumption and Lifetime Improvement", Proceedings of High Performance Computer Architecture (HPCA). 2010. (18% acceptance rate)
[VLSID2010] Yuan Xie, "Processor Architecture Design Using 3D Integration Technology. (Invited Paper)", VLSI Design, 2010. VLSID'10. 23rd International Conference on (pp. 446-451). IEEE.

2009

[SC2009] Xiangyu Dong, Naveen Muralimanohar, Norm Jouppi, Richard Kaufmann, Yuan Xie, "Leveraging 3D PCRAM Tech-nologies to Reduce Checkpoint Overhead for Future Exascale Systems", Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis, 2009, p. 57. ACM. (22% acceptance rate(59/261))
[ICCAD2009] Xiangyu Dong, Norm Jouppi, Yuan Xie, "PCRAMsim: System-Level Performance, Energy, and Area Modeling forPhase-Change RAM", Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 269-275. (26% acceptance rate(115/438))
[ICCAD2009] Balaji Vaidyanathan, Anthony S. Oates, Yuan Xie, "Intrinsic NBTI-Variability Aware Statistical Pipeline Performance Assessment and Tuning", Proceedings of International Conference on Computer-Aided Design (ICCAD). 2009. pp 164-171. (26% acceptance rate(115/438))
[IJPP2009] M. DeBole, R. Krishnan, V. Balakrishnan, W. Wang, H. Luo, Y. Wang, Y. Xie, Y. Cao and N. Vijaykrishnan, "New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components", International Journal of Parallel Programming., Vol. 37, No.4, pp.417-431, August, 2009
[IEICE-T-ELECTRON2009] Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie, "Temperature-aware NBTI Modeling Techniques in Digital Circuits", IEICE Transactions on Electronics., No. 6, pp. 875-886, 2009
[JETC2009] Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie, "Scan-chain design and optimization for three-dimensional integrated circuits", ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol.5, Issue 2, pp.1-26, July, 2009
[IEEED&T2009] Yuan Xie and Yibo Chen, "Statistical high-level synthesis under process variability", IEEE Computer Designand Test, Special Issue on HLS, Vol. 26, Issue 4, pp.78-87, July-August, 2009
[TDCS2009] R. Rajaraman, V. Degalahal, J. S. Kim, N. Vijaykrishnan, Y. Xie, M. J. Irwin, "Modeling Soft Errors at Device and Logic Level for Combinational Circuits", IEEE Transactions on Dependable and Secure Computing (TDCS)., Vol. 6, No. 3, pp.202-216, June 2009
[ISCA2009] Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie, "Hybrid Cache Architecture with Disparate Memory Technologies", Proceedings of International Symposium on Computer Architecture (ISCA), pp.34-45, June. 2009
[NOCS2009] Luca P. Carloni, Partha Pande, and Yuan Xie, "Networks-on-chip in emerging interconnect paradigms: Advantages and challenges", Proceedings of 3rd ACM/IEEE Intl. Symp. on Networks-on-chip, pp. 93-102. May. 2009
[DATE2009] Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, "Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization", Proceedings of Design Automation and Test in Europe (DATE), pp. 324-333. April. 2009
[DATE2009] Xiaoxia Wu, Jian Li, Lixi Zhang, Evan Speight, Yuan Xie, "Power and Performance of Read-write aware hybrid caches with non-volatile memories", Proceedings of Design Automation and Test in Europe (DATE), pp. 737-742. April. 2009
[ISQED2009] Balaji Vaidyanathan, Anthony Oates, Yuan Xie, Yu Wang, "NBTI-Aware Statistical Circuit Delay Assessment", Proceedings of the 2009 10th International Symposium on Quality of Electronic Design (pp. 13-18). IEEE Computer Society.
[ISQED2009] Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang, "On the efficacy of Input Vector Control to mitigate NBTI effects and leakage power", Proceedings of the 2009 10th International Symposium on Quality of Electronic Design (pp. 19-26). IEEE Computer Society.
[HPCA2009] Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen, "A novel architecture of the 3D stacked MRAM L2 cache for CMPs", Proceedings of High Performance Computer Architecture (HPCA), pp. 239-249. Feb. 2009. (19% acceptance rate(34/185))
[ICCD2009] Al Maashri, A., G. Sun, X. Dong, V. Narayanan, Y. Xie, "3D GPU Architecture using Cache Stacking: Performance, Cost, Power, and Thermal Analysis", Computer Design, 2009. ICCD 2009. IEEE International Conference on (pp. 254-259). IEEE.
[3DIC2009] Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, and Mary Jane Irwin, "Arithmetic unit design using 180nm TSV-based 3D stacking technology", 3D System Integration Conference (3DIC) 2009 (pp. 1-4). IEEE.
Yuan Xie, Jason Cong, Sachin Sapatnekar, "Three-dimensional IC: Design, CAD, and Architecture", Springer. 2009
Yuan Xie, N. Vijaykrishnan, Chita Das, "3D Network-on-chip Architecture", Three-dimensional IC: Design, CAD, and Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009
Yuan Xie, Xiangyu Dong, "System-level Cost Analsysis and Design Exploration for 3D ICs", Three-dimensional IC:Design, CAD, and Architecture. Edited by Yuan Xie, Jason Cong, Sachin Sapatnekar. Springer. 2009
[ASPDAC2009] Yibo Chen and Yuan Xie, "Tolerating Process Variations in High-Level Synthesis Using Transparent Latches", Proceedings of the 2009 Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 73-78. IEEE.

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