Most of the papers are copyrighted by ACM or IEEE. They are posted here for your personal use, to ensure timely dissemination of research work with no commercial purpose.

Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

For other papers listed below but not included in ACM digital library, I will add links to PDF as soon as possible. Or you may email me for a copy of PDF file.

2016

[MICRO2016] Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita Das, Yuan Xie, "OSCAR: Orchestrating STT-RAM Cache Traffic in Heterogeneous Architectures", 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
[MICRO2016] Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie, "A Unified Memory Network Architecture for In-Memory Computing in Commodity Servers", 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
[ISVLSI2016] Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu and Yuan Xie, "Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space", IEEE Computer Society Annual Symposium on VLSI 2016 (ISVLSI)
[TVLSI2016] Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie, "Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark Silicon Aware NoC", IEEE Transaction on Very Large Scale Integration Systems (TVLSI), 2016. 
[ISCA2016] Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, and Yuan Xie , "LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches", in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), 2016 (Acceptance rate: 54/288=19%)
[ISCA2016] Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie, "PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory", in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), 2016 (Acceptance rate: 54/288=19%) ISCA_SLIDE
[ISCA2016] Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, and Tianshi Chen, "Cambricon: An Instruction Set Architecture for Neural Networks", in Proceedings of the 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA'16), 2016. (Acceptance rate: 54/288=19%)
[ISCA2016] Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri Strukov, Yuan Xie, Frederic T. Chong, "Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs", in Proceedings of the 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA'16), 2016. (Acceptance rate: 54/288=19%)
[GLSVLSI] Peng Gu, Shuangchen Li, Dylan Stow, Russell Barnes, Liu Liu, Eren Kursun and Yuan Xie, "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges", in Great Lakes Symposium on VLSI (GLSVLSI), 2016
[TODAES2016] Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, and Yuan Xie, "TSOCKET: Thermal Sustainable Power Budgeting", ACM Trans. on Design Automation of Electronic Systems (TODAES),  2016
[TCAD2016] Ping Chi, Wang-Chien Lee, Yuan Xie, "Adapting B-plus Tree for Emerging Nov-volatile Memory Based Main Memory", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016
[TMCS2016] Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie, "Impact of Write Pulse and Process Variation on 22nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach", IEEE Transactions on Multi-Scale Computing Systems (TMCS), 2016
[ASPDAC2016] Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung Kang, Yuan Xie, "Architecture Design with STT-RAM: Opportunities and Challenges", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2016
[DAC2016] Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen, "NVSim-VXs: An Improved NVSim for Variation Aware STT-RAM Simulation", IEEE/ACM Design Automation Conference (DAC), 2016
[DAC2016] Shuangchen Li, Cong Xu, Jishen Zhao, Yu Lu, Yuan Xie, "Pinatubo: A Processing in Non-volatile Memory Architecture for Bulk Bitwise Operations", IEEE/ACM Design Automation Conference (DAC), 2016
[DAC2016] Matt Poremba, Tao Zhang, Yuan Xie, "Fine-Granularity Tile-Level Parallelism in Non-volatile Memory Architecture with Two-Dimensional Bank Subdivision", IEEE/ACM Design Automation Conference (DAC), 2016
[DATE2016] Lixue Xia, Boxun Li, Tianqi Tang, PengGu, Xiling Yin, Wenqin Huangfu, Pai-yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huangzhong Yang, "MNSIM: Simulation platform for memristor-based neuromorphic computing system", Proceedings of IEEE/ACM Design Automation and Test in Europe (DATE), 2016

2015

Ping Chi, Shuangchen Li, Peng Gu, Ziyang Qi, Cong Xu, Tao Zhang, Jishen Zhao, Yu Wang, Yongpan Liu, and Yuan Xie, "Processing-in-Memory in ReRAM-based Main Memory", SEAL-lab Technical Report - No. 2015-001 (updated 04/29/2016)
[TODAES15] Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie, "Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference", ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015
[JETC2015] Jue Wang, Yuan Xie, "A Write-Aware STTRAM-Based Register File Architecture for GPGPU", ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, No. 1, Article 6
Yuan Xie and Jishen Zhao, "Die-Stacking Architecture", Synthesis Lectures on Computer Architecture, 2015, 10(2): 1-127
Yuan Xie, Qiaosha Zou, "3D Integration Technology", More than Moore Technologies for Next Generation Computer Design. pp 23-48, Edited by Rasit Topaloglu, Springer. 2015
[TACO2015] Hsiang-yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut Kandemir, Jack Sampson, Yuan Xie, "EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors", ACM Transactions on Architecture and Code Optimization (TACO) 12.2 (2015): 17.
[TACO2015] Hsiang-yun Cheng, Mary Jane Irwin, Yuan Xie, "Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference", ACM Transactions on Architecture and Code Optimization (TACO), 2015
[CAL2015] Matt Poremba, Tao Zhang, Yuan Xie, "NVMain 2.0: Architectural Simulator to Model (Non-)Volatile Memory Systems", IEEE Computer Architecture Letters 1: 1-1.
[TODAES2015] Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie, "Impact of Cell Failure on Reliable Cross-point Resistive Memory", ACM Trans. on Design Automation of Electronic Systems (TODAES), 2015
[T-SLDM2015] Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie, "Memory and Storage System Design with Nonvolatile Memory Technologies", IPSJ Transactions on System LSI Design Methodology, Vol. 8, pp.2-11, 2/2015
[IEEED&T2015] Zhao, Jishen, Qiaosha Zou, and Yuan Xie, "Overview of 3D Architecture Design Opportunities and Techniques", IEEE Design & Test, Volume:PP, Issue: 99, 2015
[TACO2015] Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin Lim, Yuan Xie, and Paolo Faraboschi, "Buri: Scaling Big-memory Computing with Hardware-based Memory Expansion", ACM Transactions on Architecture and Code Optimization (TACO) 9.4 (2015): 39.
[DAC2015] Hsiangyun Chen, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin, "Core vs. Uncore: The Heart of Darkness", Proceedings of the 52nd Annual Design Automation Conference (DAC '15). ACM, New York, NY, USA, , Article 121 , 6 pages. 
[ICS2015] Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay Brockman, Norm Jouppi, "History-Assisted Adaptive-Granularity Caches (HAAG) for High Performance 3D DRAM Architectures", Proceedings of the 29th ACM on International Conference on Supercomputing (pp. 251-261). ACM.
[ISQED2015] Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan, "Exploring Memory Controller Configurations for Many-Core Systems with 3D Stacked DRAMs", Proceedings of 16th International Symposium on Quality Electronic Design (ISQED). pp.565-570, 2015
[ASPDAC2015] Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang, "Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis", Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific (pp. 166-171). IEEE.
[HPCA2015] Kaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yougpan Liu, Jack Sampson, Yuan Xie, Vijay Narayanan, "Architecture Exploration for Ambient Energy Harvesting Nonvolatile Processors", High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on (pp. 526-537). IEEE.
[DATE2015] Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey Vetter, Yuan Xie, "DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches", Proceedings of Design Automation and Test in Europe (DATE). pp.1543-1546, 2015
[GLSVLSI2015] Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Hai Li, Yuan Xie, Huazhong Yang, "Energy Efficient RRAM Spiking Neural Network for Real Time Classification", Proceedings of the 25th edition on Great Lakes Symposium on VLSI (pp. 189-194). ACM.
[HPCA2015] Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, "Overcoming the Challenges of Cross-Point Resistive Memory Architectures", Proceedings of the 21st IEEE Intl. Symp. on High Performance Computer Architecture (HPCA). 2015
[DAC2015] Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie, "DimNoC: A Dim Silicon Approach Towards Power-Efficient On-Chip Network", Proceedings of The 52th Design Automation Conference (DAC) , 2015
[ASPDAC2015] Yang Zheng, Cong Xu, Yuan Xie, "Modeling Framework for Cross-point Resistive Memory Design Emphasizing Reliability and Variability Issues", Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific (pp. 112-117). IEEE.
[ASPDAC2015] Qiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Junfeng Zhao, Yuan Xie, "Heterogeneous Architecture Design with Emerging 3D and Non-Volatile Memory Technologies", (Invited Paper) Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific (pp. 785-790). IEEE.

2014

[SLIP2014] Qiaosha Zou, Yuan Xie, "Compact Models and Model Standard for 2.5D and 3D Integration", Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop (pp. 1-7). ACM.
[TCAD2014] Zhan, J., Stoimenov, N., Ouyang, J., Thiele, L., Narayanan, V., & Xie, Y, "Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems", Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 33.11 (2014): 1632-1643.
[IEEED&T2014] Wulong Liu, Guoqing Chen, Yu Wang, Xue Feng, Yuan Xie, Yidong Huang, Huangzhong Yang, "Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects", IEEE Design and Test, pp.28-35, Vol. 31, No.5, Sept/Oct, 2014
[JETC2014] Wulong Liu, Yu Wang, Yuchun Man, Huangzhong Yang, Yuan Xie, "On-Chip Hybrid Power Supply System for Wireless Sensor Nodes", ACM Journal on Emerging Technologies in Computing Systems (JETC) 10.3 (2014): 23.
[TACO2014] Jue Wang, Xiangyu Dong, Yuan Xie, "Building and Optimizing MRAM-Based Commodity Memories", ACM Transactions on Architecture and Code Optimization (TACO), Volume 11, No.4, Article 36 (December 2014), 22 pages
[TACO2014] Jue Wang, Xiangyu Dong, Yuan Xie, "Preventing STT-RAM Last-Level Caches from Port Obstruction", ACM Transactions on Architecture and Code Optimization (TACO) 11.3 (2014): 23.
[TACO2014] Jue Wang, Xiangyu Dong, Yuan Xie, Norm Jouppi, "Endurance-Aware Cache Line Management for Non-Volatile Caches", ACM Transactions on Architecture and Code Optimization (TACO)11.1 (2014): 4.
[TCAD2014] Wujie Wen, Y. Zhang, Yiran Chen, Yu Wang, Yuan Xie, "PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method", IEEE Transactions on Computer Aids Design (TCAD). pp.1644-1656, Vol.33, No. 11, Nov. 2014.
[JETC2014] Jing Xie, Yang Du, and Yuan Xie, "Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology", ACM Journal on Emerging Technologies in Computing Systems (JETC),Volume 11, No.1, Article 5 (Sept 2014), 17 pages
[DAC2014] Xiaoming Chen, Yu Wang, Yun Liang, Huazhong Yang, Yuan Xie, "Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs", Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE (pp. 1-6). IEEE.

Pages