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2017

[ASPDAC2017] Wenqin Huangfu, Lixue Xia, Ming Cheng, Xiling Yin, Tianqi Tang, Boxun Li, Krishnendu Chakrabarty, Yuan Xie, Yu Wang, and Huazhong Yang, "Computation-Oriented Fault-Tolerance Schemes for RRAM Computing Systems", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2017
[ASPDAC2017] Liu Liu, Ping Chi, Shuangchen Li, Yuanqing Cheng, and Yuan Xie, "Building Energy-Efficient Multi-Level Cell STT-RAM Caches with Data Compression", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2017.
[ASPDAC2017] Kaisheng Ma, Xueqing Li, Srivatsa Rangachar Srinivasa, Yongpan Liu, John (Jack) Sampson, Yuan Xie, and Vijaykrishnan Narayanan, "Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Non-volatile Processors", Proceedings of IEEE/ACM Asia and South Paci c Design Automation Conference (ASPDAC), 2017. (Best Paper Award)
[ISCA2017] Matthew Poremba, Itir Akgun, Jieming Yin, Onur Kayiran, Yuan Xie, and Gabriel H. Loh , "There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes", Proceedings of 44th International Symposium on Computer Architecture (ISCA), 2017 (Acceptance rate: 54/322  = 16.8%)
[DATE2017] Maohua Zhu, Chao Wang, Youwei Zhuo, Wenguang Chen, and Yuan Xie, "Performance Evaluation and Optimization of HBM-Enabled GPU for Data-intensive Applications", Proceedings of IEEE/ACM Design Automation and Test in Europe (DATE), 2017.

2016

[IEEE MICRO Top Picks 2016] Kaisheng Ma, Xueqing Li, Karthik Swaminathan, Yang Zheng, Shuangchen Li, Yongpan Liu, Yuan Xie, John Jack Sampson, Vijaykrishnan Narayanan, "Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power", IEEE MICRO Top Picks, May/June 2016
[SBAC-PAD2016] Zhe Wang, Daniel A. Jim´enez, Tao Zhang, Gabriel H. Loh, Yuan Xie, "Building a Low Latency, Highly Associative DRAM Cache with the BufferedWay Predictor", 28th International Symposium on Computer Architecture and High Performance Computing
[ICCD2016] Itir Akgun, Jia Zhan and Yuan Xie, "Scalable Memory Fabric for Silicon Interposer-Based Multi-Core Systems", 34th IEEE International Conference on Computer Design (ICCD)
[ICCD2016] Peng Gu, Dylan Stow, Russell Barnes, Eren Kursun and Yuan Xie, "Thermal-aware 3D Design for Side-channel Information Leakage", 34th IEEE International Conference on Computer Design (ICCD)
[MICRO2016] Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen, "NEUTRAMS: Neural Network Transformation and Co-design under Neuromorphic Hardware Constraints", 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
[ICCAD2016] Shuangchen Li, Liu Liu, Peng Gu, Cong Xu, and Yuan Xie , "NVSim-CAM: A Circuit-Level Simulator for Emerging Nonvolatile Memory based Content-Addressable Memory", Proceedings of the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
[ICCAD2016] Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu and Yuan Xie, "Cost Analysis and Cost-Driven IP Reuse Methodology for SoC design Based on 2.5D/3D Integration ", (invited paper) Proceedings of the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
[ICCAD2016] Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang and Yuan Xie, "ODESY: A Novel 3T-3MTJ Cell Design with Optimized Area Density, Scalability and Latency", Proceedings of the 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
[MICRO2016] Jia Zhan, Onur Kayiran, Gabriel H. Loh, Chita Das, Yuan Xie, "OSCAR: Orchestrating STT-RAM Cache Traffic in Heterogeneous Architectures", 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
[MICRO2016] Jia Zhan, Itir Akgun, Jishen Zhao, Al Davis, Paolo Faraboschi, Yuangang Wang, Yuan Xie, "A Unified Memory Network Architecture for In-Memory Computing in Commodity Servers", 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) 2016
[ISVLSI2016] Dylan Stow, Itir Akgun, Russell Barnes, Peng Gu and Yuan Xie, "Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space", IEEE Computer Society Annual Symposium on VLSI 2016 (ISVLSI)
[TVLSI2016] Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie, "Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark Silicon Aware NoC", IEEE Transaction on Very Large Scale Integration Systems (TVLSI), 2016. 
[ISCA2016] Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, and Yuan Xie , "LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches", in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), 2016 (Acceptance rate: 54/288=19%)
[ISCA2016] Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie, "PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory", in Proceedings of the 43rd International Symposium on Computer Architecture (ISCA), 2016 (Acceptance rate: 54/288=19%) ISCA_SLIDE
[ISCA2016] Shaoli Liu, Zidong Du, Jinhua Tao, Dong Han, Tao Luo, Yuan Xie, Yunji Chen, and Tianshi Chen, "Cambricon: An Instruction Set Architecture for Neural Networks", in Proceedings of the 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA'16), 2016. (Acceptance rate: 54/288=19%)
[ISCA2016] Lunkai Zhang, Brian Neely, Diana Franklin, Dmitri Strukov, Yuan Xie, Frederic T. Chong, "Mellow Writes: Extending Lifetime in Resistive Memories through Selective Slow Write Backs", in Proceedings of the 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA'16), 2016. (Acceptance rate: 54/288=19%)
[GLSVLSI] Peng Gu, Shuangchen Li, Dylan Stow, Russell Barnes, Liu Liu, Eren Kursun and Yuan Xie, "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges", in Great Lakes Symposium on VLSI (GLSVLSI), 2016
[TODAES2016] Guoqing Chen, Yi Xu, Xing Hu, Xiangyang Guo, Jun Ma, Yu Hu, and Yuan Xie, "TSOCKET: Thermal Sustainable Power Budgeting", ACM Trans. on Design Automation of Electronic Systems (TODAES),  2016
[TCAD2016] Ping Chi, Wang-Chien Lee, Yuan Xie, "Adapting B-plus Tree for Emerging Nov-volatile Memory Based Main Memory", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016
[TMCS2016] Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie, "Impact of Write Pulse and Process Variation on 22nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach", IEEE Transactions on Multi-Scale Computing Systems (TMCS), 2016
[ASPDAC2016] Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung Kang, Yuan Xie, "Architecture Design with STT-RAM: Opportunities and Challenges", Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2016
[DAC2016] Enes Eken, Linghao Song, Ismail Bayram, Cong Xu, Wujie Wen, Yuan Xie, Yiran Chen, "NVSim-VXs: An Improved NVSim for Variation Aware STT-RAM Simulation", IEEE/ACM Design Automation Conference (DAC), 2016
[DAC2016] Shuangchen Li, Cong Xu, Jishen Zhao, Yu Lu, Yuan Xie, "Pinatubo: A Processing in Non-volatile Memory Architecture for Bulk Bitwise Operations", IEEE/ACM Design Automation Conference (DAC), 2016
[DAC2016] Matt Poremba, Tao Zhang, Yuan Xie, "Fine-Granularity Tile-Level Parallelism in Non-volatile Memory Architecture with Two-Dimensional Bank Subdivision", IEEE/ACM Design Automation Conference (DAC), 2016
[DATE2016] Lixue Xia, Boxun Li, Tianqi Tang, PengGu, Xiling Yin, Wenqin Huangfu, Pai-yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huangzhong Yang, "MNSIM: Simulation platform for memristor-based neuromorphic computing system", Proceedings of IEEE/ACM Design Automation and Test in Europe (DATE), 2016

2015

Ping Chi, Shuangchen Li, Peng Gu, Ziyang Qi, Cong Xu, Tao Zhang, Jishen Zhao, Yu Wang, Yongpan Liu, and Yuan Xie, "Processing-in-Memory in ReRAM-based Main Memory", SEAL-lab Technical Report - No. 2015-001 (updated 04/29/2016)
[TODAES15] Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie, "Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference", ACM Transactions on Design Automation of Electronic Systems (TODAES), 2015
[JETC2015] Jue Wang, Yuan Xie, "A Write-Aware STTRAM-Based Register File Architecture for GPGPU", ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, No. 1, Article 6
Yuan Xie and Jishen Zhao, "Die-Stacking Architecture", Synthesis Lectures on Computer Architecture, 2015, 10(2): 1-127
Yuan Xie, Qiaosha Zou, "3D Integration Technology", More than Moore Technologies for Next Generation Computer Design. pp 23-48, Edited by Rasit Topaloglu, Springer. 2015
[TACO2015] Hsiang-yun Cheng, Mary Jane Irwin, Yuan Xie, "Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference", ACM Transactions on Architecture and Code Optimization (TACO), 2015
[TACO2015] Hsiang-yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut Kandemir, Jack Sampson, Yuan Xie, "EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors", ACM Transactions on Architecture and Code Optimization (TACO) 12.2 (2015): 17.
[CAL2015] Matt Poremba, Tao Zhang, Yuan Xie, "NVMain 2.0: Architectural Simulator to Model (Non-)Volatile Memory Systems", IEEE Computer Architecture Letters 1: 1-1.
[TODAES2015] Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie, "Impact of Cell Failure on Reliable Cross-point Resistive Memory", ACM Trans. on Design Automation of Electronic Systems (TODAES), 2015
[IEEED&T2015] Zhao, Jishen, Qiaosha Zou, and Yuan Xie, "Overview of 3D Architecture Design Opportunities and Techniques", IEEE Design & Test, Volume:PP, Issue: 99, 2015
[TACO2015] Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin Lim, Yuan Xie, and Paolo Faraboschi, "Buri: Scaling Big-memory Computing with Hardware-based Memory Expansion", ACM Transactions on Architecture and Code Optimization (TACO) 9.4 (2015): 39.
[T-SLDM2015] Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie, "Memory and Storage System Design with Nonvolatile Memory Technologies", IPSJ Transactions on System LSI Design Methodology, Vol. 8, pp.2-11, 2/2015
[DAC2015] Hsiangyun Chen, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin, "Core vs. Uncore: The Heart of Darkness", Proceedings of the 52nd Annual Design Automation Conference (DAC '15). ACM, New York, NY, USA, , Article 121 , 6 pages. 
[ICS2015] Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay Brockman, Norm Jouppi, "History-Assisted Adaptive-Granularity Caches (HAAG) for High Performance 3D DRAM Architectures", Proceedings of the 29th ACM on International Conference on Supercomputing (pp. 251-261). ACM.
[ISQED2015] Fen Ge, Jia Zhan, Yuan Xie, Vijaykrishnan Narayanan, "Exploring Memory Controller Configurations for Many-Core Systems with 3D Stacked DRAMs", Proceedings of 16th International Symposium on Quality Electronic Design (ISQED). pp.565-570, 2015
[ASPDAC2015] Shuangchen Li, Ang Li, Yongpan Liu, Yuan Xie, Huazhong Yang, "Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis", Design Automation Conference (ASP-DAC), 2015 20th Asia and South Pacific (pp. 166-171). IEEE.
[HPCA2015] Kaisheng Ma, Yang Zheng, Shuangchen Li, Karthik Swaminathan, Xueqing Li, Yougpan Liu, Jack Sampson, Yuan Xie, Vijay Narayanan, "Architecture Exploration for Ambient Energy Harvesting Nonvolatile Processors", High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on (pp. 526-537). IEEE.
[DATE2015] Matt Poremba, Sparsh Mittal, Dong Li, Jeffrey Vetter, Yuan Xie, "DESTINY: A Tool for Modeling Emerging 3D NVM and eDRAM caches", Proceedings of Design Automation and Test in Europe (DATE). pp.1543-1546, 2015
[GLSVLSI2015] Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Hai Li, Yuan Xie, Huazhong Yang, "Energy Efficient RRAM Spiking Neural Network for Real Time Classification", Proceedings of the 25th edition on Great Lakes Symposium on VLSI (pp. 189-194). ACM.
[HPCA2015] Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, "Overcoming the Challenges of Cross-Point Resistive Memory Architectures", Proceedings of the 21st IEEE Intl. Symp. on High Performance Computer Architecture (HPCA). 2015

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